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| ANALOG IP BLOCK FLASH6 - CMOS 6-Bit FLASH A/D CONVERTER DATA SHEET PROCESS C35B3 (0.35um) DESCRIPTION The FLASH6 is a complete analog to digital converter cell which operates from a single supply. It performs sampling, analog-to-digital conversion, generating a 6 bit value in parallel form. The output word rate can be up to 100MS/s. The output data format is compatible with most P and digital signal processors. FEATURES ! ! ! ! ! ! ! ! Small Area < 0.257 mm2 Size x= 361 m y= 710 m Supply Voltage 3.0-3.6 V Junction Temp. Range -40 - 125C Resolution 6-Bit Maximum Sampling Rate 100MS/s Low Input Capacitance < 5pF Output Code Binary VREFP VREFN IB IA S R e s is to r L a d d e r PD O VL C o m p a ra t o rs V IN VDD A E rro r C o rre c tio n /R O M /O u tp u t L a tc h VSSA T im in g VD D 6 B it B u s VSS STROBE C LK D AT A<0> D AT A<1> D AT A<2> D AT A <3> D A T A<4> D AT A<5> Revision B, 07.09.02 Page 1 of 9 Data Sheet : FLASH6 - C35 TECHNICAL DATA (Tjunction = -40 to 125 C, VDDA=VDD=+3.0V to +3.6V, fclk = 100MHz, VREFP and VREFN as specified, pad resistors as specified in the functional block diagram, unless otherwise specified) DC ACCURACY Symbol DNL INL OFF GAINERR Parameter Resolution (No missing Code) Differential Linearity Error Integral Linearity Error Offset Error Gain Error Conditions Min 6 -0.8 -0.8 -2 -2 Typ 6 0.4 0.4 Max 6 +0.8 +0.8 +2 +2 Units Bit LSB LSB LSB LSB CHARACTERISTICS Symbol IBIAS Parameter Bias sink current Conditions Min Typ 30 Max Units uA REFERENCE CHARACTERISTICS Symbol VREFP VREFN VREF Rref TKRref Parameter Pos. Reference Voltage Neg. Reference Voltage Difference between VRP and VRN Reference Impedance 1) Conditions Min 1.8 0.35 1.2 Typ 2.4 0.4 2 380 1.2 Max 2.8 0.6 2.45 Units V V V Ohm mOhm/K VREFP-VREFN ANALOG INPUT Symbol Vin Rin Cin Parameter Input Voltage Range Input Impedance Conditions Min VREFN 100 5 Typ Max VREFP Units V MOhms pF AC ACCURACY (VREFP=2.4V, VREFN=0.4V) Symbol THD THD SFDR SFDR SNR SNR SINAD SINAD ENOB ENOB Parameter Total Harmonic Distortion Total Harmonic Distortion Spurious Free Dynamic Range Spurious Free Dynamic Range Signal to Noise Ratio Signal to Noise Ratio Signal to (Noise+Dist.) Ratio Signal to (Noise+Dist.) Ratio Effective Number of Bits Effective Number of Bits Conditions fin=1MHz fin=30MHz fin=1MHz fin=30MHz fin=1MHz fin=30MHz fin=1MHz fin=30MHz fin=1MHz fin=30MHz Min Typ -41.3 -41.3 46.2 46.2 35.88 34.1 34.8 33.3 5.5 5.24 Max Units dB dB dB dB dB dB dB dB Bit Bit 1) VREFP to VREFN Revision B, 07.09.02 Page 2 of 9 Data Sheet : FLASH6 - C35 DIGITAL INPUTS AND OUTPUTS Symbol VDD VSS VIL VIH VOL VOH Digital Output Level Parameter Pos. digital Supply Voltage Neg. digital Supply Voltage Digital Input Level Conditions VDD=VDDA VSS=VSSA Min 3.0 0 VSS 0.7*VDD VSS VDD Typ 3.3 0 Max 3.6 0 0.3*VDD VDD Units V V V V V V POWER REQUIREMENTS Symbol VDDA VSSA IDD 1) 3) 1) 3) Parameter Pos. analog Supply Voltage Neg. analog Supply Voltage Supply Current Digital Supply Current Analog Supply Power Consumption Power Up Mode Reference Current Total Power Consumption Total Power Consumption Power Down Mode Conditions VDD=VDDA VSS=VSSA Min 3.0 0 Typ 3.3 0 7.5 4 38 Max 3.6 0 15 8 82,8 10 118,8 60 Units V V m mA mW mA mW mW IDDA Psup 1) 3) IREF 1) 3) Pdiss_tot 1) 3) Pdiss_pd 2) 3) incl. Ref. 5 54,5 30 TIMING CHARACTERISTICS Symbol 1/Tconv fclk Tdap Tconv Tpwhclk Tpwlclk Jclk Tdcs Tsuds Tdp Twakeupall Twakeup Parameter Conversion Rate Master CLOCK Frequency Aperture Delay Total Conversion Time CLOCK Pulse width High CLOCK Pulse width Low CLOCK Jitter Delay Time CLOCK to STROBE Setup Time DATA to STROBE Delay Time Pipeline Wake up Time all Wake up Time 5.5 0.8 1 50 Twkupall Tdap 5 5 Conditions Min 0.1 0.1 Typ 80 80 1.8 1 6.5 6.5 1*e-3/fin Max 100 100 Units MS/sec MHz ns clk cycle nsec nsec sec nsec nsec nsec nsec nsec 1) 2) 3) Measured during a conversion with 100MHz clock frequency. After 10s power down. The measurement includes 8 digital (8mA) output pads. Revision B, 07.09.02 Page 3 of 9 Data Sheet : FLASH6 - C35 CODE TABLE 1LSB = (VREFP - VREFN) / 64. Output Code 00 0000 00 0001 00 0010 ... 11 1111 Input Voltage: VIN-VINB VREFN.....0.5LSB 0.5LSB.....1.5LSB 1.5LSB.....2.5LSB ... 62.5LSB.....VREFP Revision B, 07.09.02 Page 4 of 9 Data Sheet : FLASH6 - C35 TYPICAL PERFORMANCE CHARACTERISTICS (Tjunction=25C, VDDA=VDD=+3.3V, fclk=100MHz, VREFP=+2.4V and VREFN=0.4V, unless otherwise specified) DNL [LSB] Digital Code INL [LSB] Digital Code DNL INL FFT [dBc] Input Signal Frequency [Hz] FFT [dBc] Input Signal Frequency [Hz] Spectrum @1MHz 1) Spectrum @30MHz 1) ENOB [Bit] ENOB [Bit] pg VREFP-VREFN [V] Input Signal Frequency [Hz] ENOB vs (VREFP-VREFN) @30MHz ENOB vs Input Signal Frequency 1) The spectrum consists of 1024 pins Revision B, 07.09.02 Page 5 of 9 Data Sheet : FLASH6 - C35 SYMBOL VDDA VREFP A D VREFN IBIAS 6 DATA<5:0> VDD PINLIST Pin VIN VREFP VREFN IBIAS PD Description Input Voltage Pos. Reference Voltage Neg. Reference Voltage Bias Current Power down Signal Master Clock Data Output (DATA<5>=MSB) Overload Data Strobe Signal Pos. Analog Supply Neg. Analog Supply Connect to VSSA Pos. Digital Supply Neg. Digital Supply Typ AIN AIN AIN AIN DIN 0.1pF Cap 5pF VIN CLK DIN DOUT DOUT DOUT S S S S S 0.1pF FLASH6 PD OVL CLK STROBE DATA<5:0> OVL STROBE VDDA SHIELD VSSA VSS VSSA SHIELD VDD VSS THEORY OF OPERATION The Macro Cell FLASH6 is a 6-bit single step parallel analog to digital converter. The architecture is based on a 380 Ohm polysilicon resistor reference ladder and static CMOS comparators. The thermometer code of the comparator outputs is encoded in a fast ROM encoder into straight binary code with CMOS logic signal levels. The last comparator output is connected unlatched to the OVL output. The area of the converter is small. The comparators do not need auto zeroing and therefore are fast and perform minimal kickback on the analog signal input. The conversion range is set by the reference inputs VREFP and VREFN. The output OVL indicates an overload condition when Vin > (VREFP - 0.5*LSB). recommended to wire them on chip to separated pins, especially when the block is embedded in a large digital circuit. The supplies may then be connected together on PC-board level. The proper use of blocking capacitors in the application is important REFERENCE VOLTAGE Both input pads VREFP and VREFN must have a 0 Ohm protection resistor. The ESD test was performed with 1kV (Norm: MIL 883 E method 3015). The proper use of blocking capacitors in the application is important ! POWER SUPPLIES The converter requires a single +3.3V power supply. The supplies for analog and digital are separated and may be connected together. However, for maximum noise immunity it is INPUT VOLTAGE The input pad VIN must have a 0 Ohm protection resistor. The ESD test was performed with 1kV (Norm: MIL 883 E method 3015). Revision B, 07.09.02 Page 6 of 9 Data Sheet : FLASH6 - C35 FUNCTIONAL BLOCK DIAGRAM FLASH6 VIN OVL VREFP Rref . . . . . . . . . E R R O R C O R R. VDDA VSSA ROM VDD VSS VREFN PD IBIAS CLK LATCH 6 DATA<5:0> TIMING STR TIMING DIAGRAM OF FLASH6 Sample N Sample N+1 Vin Sample N+2 Tdap Tdcs Tpwlclk Tpwhclk CLK STROBE DATA<0:5> Sample N-2 Sample N-1 Sample N Tsuds Revision B, 07.09.02 Page 7 of 9 Data Sheet : FLASH6 - C35 TYPICAL APPLICATION +3.3V VDDA 10uF 100nF 15nF 1.2nF 0.47pF 0.22pF +3.3V VDD 10uF 100nF 15nF 1.2nF 0.47pF 0.22pF +3.3V +3.3V VDDA VSSA VSS VREFP VIN VIN 3) A D VDD 6 DATA<5:0> VREFN IBIAS 2.4V 2) 2.5nF 1) 1) 0.1nF 30pF 1) 0.4V 2) 2.5nF 1) 1) 1) FLASH6 PD CLK 30uA 3) 0.1nF 30pF OVL STROBE SHIELD VSSA 0.3nF 50pF 0.3nF 50pF 1.4V 1) 63pF GROUND Configuration: Continuous Conversion at 100MS/sec 1) 1) The value of the capacitor depends on the input frequency. For SMD capacitors use the type NPO and for normal capacitors use the type MKT for best performance. 2) The accuracy for both reference voltages must be higher than the resolution of the ADC. In the typical application both voltages are filtered by a second order low pass filter (fc=5Hz) and buffered with an AD711. 3) The accuracy for the input voltage must be higher than the resolution of the ADC. In the typical application the input voltage is filtered by a seven order low pass filter (fc=32MHz) and buffered with a THS3001. Revision B, 07.09.02 Page 8 of 9 VSS 1) 1) 1) 1) 100MHz Data Sheet : FLASH6 - C35 Contact austriamicrosystems AG A 8141 Schloss Premstatten, Austria T. +43 (0) 3136 500 5333 F. +43 (0) 3136 500 5755 support@austriamicrosystems.com Copyright Copyright (c) 2002 austriamicrosystems. Trademarks registered (R). All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. To the best of its knowledge, austriamicrosystems asserts that the information contained in this publication is accurate and correct. Revision B, 07.09.02 Page 9 of 9 |
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